ACU Hardware

The Array Control Unit has responsibility for primary control of the IUA. It consists of a Control Processor (CP), in which user programs are run, and a micro controller (uC) that is used to generate the SIMD instruction stream for the CAAPP.

Control Processor

The Control Processor consists of a SPARC (TM) processor, its local memory, and the SPARC Sbus. The local memory is used for program and data and may be from 16 MB to 64 MB. See software for a detailed description of the CP software.

The CP provides two major functions: control of the CAAPP and synchronization of the IUA.

The user program running in the CP generates information for the Micro Engine and places this information on a FIFO queue called the processor FIFO or pFIFO. This information is interpreted by the Micro Engine to produce the instruction stream for the SIMD processors of the CAAPP. The CP must load the microcode for the Micro Engine.

The CP is able to read data sent back to it by accessing the count FIFO queue (cFIFO). The CP is also able to access other status information from the Micro Engine.

The CP is able to access the ICAP Shared memory (ISM) using the VME Bus. The CP may also load images into the HCSM or access data stored there.

Micro Controller

The Micro Controller (uC) is composed of a Micro Engine in which microcode is used to generate the CAAPP instruction stream, a Post Processor used for timing, and associated FIFO queues used for rate buffering.

Micro Engine

The Micro Engine is a very long instruction word (128 bits) micro processor that was designed specifically to generate the bit-serial instruction stream for the CAAPP. The Micro Engine reads information from the pFIFO queue and interprets it to determine what CAAPP instructions to generate. These instructions are broadcast to every CAAPP processing element (PE). The pFIFO provides rate buffering between the CP and the Micro Engine.

The CAAPP instruction stream is placed on the instruction FIFO queue (iFIFO) where it is read by the Post Processor.

Post Processor

The post processor is responsible for ensuring that an uninterrupted instruction stream is sent to the CAAPP. If the iFIFO is empty, the Post Processor sends a NOP instruction. Otherwise, it sends the instruction at the front of the iFIFO queue. The iFIFO provides rate buffering between the Micro Engine and the Post Processor.

Some instructions placed on the iFIFO are executed directly by the Post Processor and not relayed to the CAAPP. These instructions are used to:

Synchronize the Micro Engine and the Post Processor.
Synchronize the Micro Engine and the CAAPP.
Instruct the Post Processor to generate status information to be placed on the cFIFO queue from the Global Response and other status.