IUA Hardware

An IUA system, as depicted above, consists of several processors, memories, and devices. The main component is the IUA Processor board. An IUA may contain from one to eight of these boards connected on the IUA extended VME Bus. An IUA also contains one ACU Processor Board which provides the central control of the IUA system.

Each IUA Processor board contains two Quadnodes. Each Quadnode contains eight nodes. Each node contains 256 SIMD processors and one MIMD processor.

The SIMD processors are arranged in a rectangular grid. This grid may be of size 64 x 32 to 128 x 128. The SIMD processors are connected in a mesh communications grid and in the Coterie Network.

The MIMD processors are also arranged in a rectangular grid which may be of size 4 x 2 to size 8 x 8. The MIMD processors (IPE) are very powerful, full computers. The MIMD processors, in a quadnode, are connected together by a ring network and with shared memory. The Quadnodes are connected together by a full inter-connect network.

The IUA is connected to a Host over ethernet. The Host supports a file system and other I/O devices. The Host provides limited I/O. For high-bandwidth I/O, other I/O components may be available:

There may be other computers attached to the IUA VME Bus. These Attached Processors (AP) may perform high-level knowledge-based vision operations or operations unrelated to vision processing.

Other devices may be connected to the IUA VME Bus such as DataCube boards for image acquisition and display.

IUA Board

Two quadnodes reside on one IUA Processor board. There is no unique relationship between these two quadnodes except that the communications between them are routed on the board and do not utilize the IUA backplane.


The nodes of a quadnode share a memory on the Quadnode Global Bus. The ICAP Processing Elements (IPEs) at the MIMD level are connected in a ring network. The ISM (ICAP Shared Memory) is a set of memories accessible to other processors over the IUA VMEbus. However, the IPEs on the quadnode may access only the ISM that is on that same quadnode through the Quadnode Global Bus.


The CAAPP is a grid of simple processing elements (PEs) that each execute the same instruction at the same time and are used primarily for low level image understanding tasks. Each node contains one CAAPP chip containing 256 simple bit-serial SIMD processors.

Along with the CAAPP chip is an ICAP Processing Element (IPE). The ICAP is a tightly coupled network of independent processing elements (IPEs) used for intermediate-level symbolic operations. Each IPE has its own private data and program memory (IPM).

The HCSM (Host CAAPP Shared Memory) provides a memory into which images may be transferred at a high rate and accessed by the CAAPP. The CISM (CAAPP ICAP Shared Memory) is the primary memory for the CAAPP. The CAAPP can communicate with the IPE through the dual-ported CAAPP ICAP Shared Memory (CISM).

Array Control Unit

The ACU (Array Control Unit) contains the user-programmable Control Processor (CP) that exercises primary control of the IUA, and the Micro Controller (uC) that generates instructions for the CAAPP.

IUA Documentation

IUA Glossary

IUA Software

IUA Home Page

IUA Outline